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Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Dual differential 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Output frequency range: 20.83MHz to 500MHz * Crystal input frequency range: 14MHz to 27MHz * VCO range: 250MHz to 500MHz * Parallel or serial interface for programming counter and output dividers * RMS period jitter: 6ps (maximum) * Cycle-to-cycle jitter: 30ps (maximum) * Supply voltage modes: 3.3/3.3/3.3 3.3/3.3/2.5 * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8430I-61 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High FreHiPerClockSTM quency Synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8430I-61 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 500MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. Frequency steps as small as 1MHz can be achieved using a 16MHz crystal or TEST_CLK.
ICS
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL_IN OSC XTAL_OUT
/ 16
PIN ASSIGNMENT
XTAL_OUT VCO_SEL nP_LOAD
M4
M3
M2
M1
M0
0
32 31 30 29 28 27 26 25
1
M5 M6 M7
/1 /1.5 /2 /3 /4 /6 /8 /12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
24 23 22
XTAL_IN TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
M8 N0 N1 N2
FOUT0 nFOUT0 FOUT1 nFOUT1
ICS8430I-61
21 20 19 18 17
PLL
PHASE DETECTOR
MR
VCO /M
0 1
VEE
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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REV. A OCTOBER 21, 2004
Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 250 M 500. The frequency out is defined as follows: fout = fVCO = fxtal x M N N 16 Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430I-61 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 500MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8430I-61 support two input modes and to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hard-wired to set the M divider and N output divider to a
T1 0 0 1 1
T0 0 1 0 1
TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS Fout
SERIAL LOADING
S_CLOCK
S_DATA S_LOAD
T1
t
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N2 nP_LOAD
M, N
t
S
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Input Power Output Power Output Power Output Description
TABLE 1. PIN DESCRIPTIONS
Number 28, 29, 30 31, 32, 1, 2 3, 4 5, 7 6 8, 16 9 10 11, 12 13 14, 15 Name M0, M1, M2 M3, M4, M5, M6 M7, M8 N0, N2 N1 V EE TEST VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. Pullup Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS interface levels. Core supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When Logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between cr ystal oscillator or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N2:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels.
17
MR
Input
Pulldown
18 19 20 21 22 23 24, 25 26 27
S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL_IN, XTAL_OUT nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown
Pulldown Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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REV. A OCTOBER 21, 2004
Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. X X L L L H
MR H L L L L L L
nP_LOAD X L H H H H
M X Data Data X X X X
N X Data Data X X X X
S_LOAD
L H X X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 250 251 252 253 * * 498 499 500 M Divide 250 251 252 253 * * 498 499 500 256 M8 0 0 0 0 * * 1 1 1 128 M7 1 1 1 1 * * 1 1 1 64 M6 1 1 1 1 * * 1 1 1 32 M5 1 1 1 1 * * 1 1 1 16 M4 1 1 1 1 * * 1 1 1 8 M3 1 1 1 1 * * 0 0 0 4 M2 0 0 1 1 * * 0 0 1 2 M1 1 1 0 0 * * 1 1 0 1 M0 0 1 0 1 * * 0 1 0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N2 0 0 0 0 1 1 1 1
8430AYI-61
N1 0 0 1 1 0 0 1 1
N0 0 1 0 1 0 1 0 1
N Divider Value 1 1.5 2 3 4 6 8 12
Output Frequency (MHz) Minimum 250 166.66 125 83.33 62.5 41.66 31.25 20.83 Maximum 500 333.33 250 166.66 125 83.33 62.5 41.66
REV. A OCTOBER 21, 2004
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ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO I EE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 155 55 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter M0:M8, N0:N2, MR, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, VCO_SEL, XTAL_SEL TEST_CLK M0:M8, N0:N2, MR, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, VCO_SEL, XTAL_SEL TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL VOH VOL Output High Voltage Output Low Voltage TEST; NOTE 1 TEST; NOTE 1 Test Conditions Minimum 2 2 -0.3 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 150 5 Units V V V V A A A
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
-150 2.6 0.5
A V V
NOTE 1: Outputs terminated with 50 to VCCO/2.
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500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VOH V OL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section, "3.3V Output Load Test Circuit" figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter TEST_CLK; NOTE 1 fIN Input Frequency XTAL_IN XTAL_OUT NOTE 1 Test Conditions Minimum 14 14 Typical Maximum 27 27 Units MHz MHz
S_CLOCK 50 MHz NOTE 1: For the input cr ystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 500MHz range. Using the minimum input frequency of 14MHz, valid values of M are 286 M 511. Using the maximum input frequency of 27MHz, valid values of M are 149 M 296.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 14 Test Conditions Minimum Typical Maximum 27 50 7 Units MHz pF Fundamental
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol FOUT Parameter Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 4 Period Jitter, RMS; NOTE 1, 3 Output Skew; NOTE 2, 4 Output Rise/Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD odc tLOCK Output Duty Cycle PLL Lock Time Even N divides Odd N divides 20% to 80% 200 5 5 5 5 5 5 48 45 52 55 1 N 1.5 N = 1.5 Test Conditions Minimum 20.83 Typical Maximum 500 30 100 6 15 700 Units MHz ps ps ps ps ps ns ns ns ns ns ns % % ms
tjit(cc) tjit(per) tsk(o)
tR / tF
All AC parameters guaranteed for VCC=VCCA=VCCO=3.3V 5%. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: N divide = 1.5 characterized using the Wavecrest tailfit algorithm. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A OCTOBER 21, 2004
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ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC, VCCA, VCCO
Qx
SCOPE
nFOUTx FOUTx nFOUTy FOUTy
LVPECL
VEE
nQx
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH VREF VOL
nFOUTx FOUTx
tcycle
n
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
tjit(cc) = tcycle n -tcycle n+1
Histogram
Reference Point
(Trigger Edge)
1000 Cycles
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx 80% Clock Outputs 80% VSW I N G 20% tR tF
odc = t PW t PERIOD
FOUTx
Pulse Width t
PERIOD
20%
OUTPUT RISE/FALL TIME
8430AYI-61
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
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ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8430I-61 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10 F 10
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. A OCTOBER 21, 2004
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ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS8430I-61 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm
XTAL_IN
C1 22p
X1 18pF Parallel Cry stal
XTAL_OUT
C2 22p
ICS84332 ICS8430I-61
Figure 4. CRYSTAL INPUt INTERFACE
LAYOUT GUIDELINE
The schematic of the ICS8430I-61 layout example used in this layout guideline is shown in Figure 5A. The ICS8430I-61 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
C1
X1
C2
U1
M4 M3 M2 M1 M0 VCO_SEL nP_LOAD XTAL_OUT
32 31 30 29 28 27 26 25
VCC
1 2 3 4 5 6 7 8
M5 M6 M7 M8 N0 N1 N2 VEE
XTAL_IN REF_IN nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR
24 23 22 21 20 19 18 17
REF_IN XTAL_SEL
R7 10
VCCA
S_LOAD S_DATA S_CLOCK
C11 0.01u
C16 10u
9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16
8430-61
TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE
VCC
VCC
R1 125
R3 125
Zo = 50 Ohm
IN+
C14 0.1u
TL1
C15 0.1u
+
IN-
Zo = 50 Ohm TL2
R2 84
R4 84
-
FIGURE 5A. SCHEMATIC
8430AYI-61
OF
RECOMMENDED LAYOUT
REV. A OCTOBER 21, 2004
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
* The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 24 (XTAL_IN) and 25 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
GND
C1 C2
VCC VIA
X1 U1
PIN 1
C11 C16 VCCA R7
Close to the input pins of the receiver
C14
TL1N
C15
TL1
R1
R2
TL1N
TL1 TL1, TL21N are 50 Ohm traces and equal length
R3
R4
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8430I-61
8430AYI-61
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REV. A OCTOBER 21, 2004
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ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430I-61. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8430I-61 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.597W * 42.1C/W = 110.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8430AYI-61
www.icst.com/products/hiperclocks.html
12
REV. A OCTOBER 21, 2004
Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430I-61 is: 4258
8430AYI-61
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 21, 2004
Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8430AYI-61
www.icst.com/products/hiperclocks.html
14
REV. A OCTOBER 21, 2004
Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Marking ICS8430AYI-61 ICS8430AYI-61 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS8430AYI-61 ICS8430AYI-61T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8430AYI-61
www.icst.com/products/hiperclocks.html
15
REV. A OCTOBER 21, 2004
Integrated Circuit Systems, Inc.
ICS8430I-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Description of Change Features Section - changed Supply Voltage bullet. AC Table - Added 3V Note. Date 10/21/04
Rev A
Table T7
Page 1 6
8430AYI-61
www.icst.com/products/hiperclocks.html
16
REV. A OCTOBER 21, 2004

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